As a memory accessed by multiple central processing units (CPUs), multi-port memory that includes multiple memory banks each capable of storing data and multiple input and output ports is conventionally known. A technique of using a memory controller as an apparatus to control memory when a CPU reads and writes data with respect to the memory is also known. Another technique is disclosed according to which a buffer mechanism is provided between memory and a bus or between a CPU and a bus, and a memory controller has a function of automatically branching data to a given port, in addition to a function of temporarily causing data to be retained in the buffer, (see, e.g., Published Japanese-Translation of PCT Application, Publication No. H11-510285).
A further technique is disclosed according to which a path for requests and that for responses are separated from each other, and a CPU is enabled to immediately proceed to the next process by a mechanism consequent to a memory controller that controls a multi-port memory immediately sending back a dummy response in response to a request from the CPU (see, e.g., Japanese Laid-Open Patent Publication No. 2008-117109).
A technique is disclosed as a technique of using multiple ports according to which address spaces are divided among the function types and a port is prepared for each group of address spaces, whereby multiple functions can be concurrently be executed and processes can be executed at a high speed (see, e.g., Japanese Laid-Open Patent Publication No. 2003-114797).
Among the conventional techniques, the technique according to Japanese Laid-Open Patent Publication No. H11-510285 enables minimization of latency on the paths by setting the clock to be high between the memory and the buffer and between the bus and the buffer. However, a problem arises in that power consumption increases consequent to setting the clock to be high. A problem also arises in the technique according to Japanese Laid-Open Patent Publication No. 2008-117109 in that access contention still continues to occur even when the path for requests and that for responses are separated from each other. Another problem also arises in that power consumption increases because the clock becomes high between the bus and the buffer, similarly to the technique according to Japanese Laid-Open Patent Publication No. H11-510285.
A problem arises in the technique according to Japanese Laid-Open Patent Publication No. 2003-114797 in that access contention occurs when software, each having a function different from the other, access the same address space. A port needs to be prepared for each type of function and the number of ports increases as of the number of function types increases. Therefore, another problem arises in that power consumption increases.